Prior art solid state power control systems have generally required that the power switch be connected in the neutral leg of the power supply. A few systems using minority carrier switch devices such as, for example, P-channel MOSFETs, have allowed the power switch to be connected in the high side of the line; however, the size and power dissipation of such minority carrier devices has been excessive. For this reason, it has been found desirable to use majority carrier devices, such as, for example, N-channel MOSFETs or the like, due to their small size lower cost and low power dissipation and to design a means for allowing connection of the same in the high side of the line.
The typical placement of an N-type power device is the neutral side of a DC supply since the N-type devices require that a positive voltage bias or control voltage be provided between the gate and source for a FET or between the base and emitter for a bipolar transistor. Typical drive circuits of this type are shown in International Rectifier's 1982-1983 Databook, FIGS. 17, 18 and 19 on page A-46. Circuits for supplying gate drive voltage when the power switching device is in the line side or high voltage side are shown in FIGS. 20, 21, 22 and 23 of the aforementioned Databook on pages A-46 and A-47. Each of these circuits requires either a separate gate supply, a low duty cycle or excessive leakage to the load when the device is off since the supply is returned only to the FET source terminal. For these reasons, it has been accepted practice to use P-type switch devices that require a negative gate bias voltage, either FETs or bipolar transistors, when a ground connected load is desired. P-channel MOSFET circuits are shown in International Rectifier's 1982-1983 Databook, FIGS. 1 through 3(b), pages A-60 and A-61.
To overcome the aforementioned handicaps of the prior art circuits, this invention relates to improvements thereover. Because of its low RDS(on) of drain-to-source resistance in the on condition, an N-channel FET is the desirable FET switching device in low voltage DC power controller applications as compared with the P-channel FET. However, the gating means is complicated since the gate voltage must rise about 15 volts above its source terminal voltage which rises near or to about 28 volts (the supply voltage level) when the FET is fully on. This problem is overcome by the invention in an efficient and economical manner.